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LH155BA
LH155BA
DESCRIPTION
The LH155BA is an LCD driver with a built-in RAM suitable for driving medium/small scale dot-matrix LCD panels, and which is capable of being directly connected to the bus line of a microcomputer. The LH155BA stores in the RAM the 8-bit parallel or serial display data transferred from the microcomputer and generates LCD drive signals. Since the LH155BA features a bit-map type LCD driver that one bit of data in the display RAM corresponds to one dot in the LCD, there is a lot of freedom in displaying. The LH155BA has 128 segment outputs and 64 common outputs in a single chip, making it possible to create an LCD system with the fewest number of the chips. The LH155BA enables an LCD system for batteryoperated, hand-carrying information equipment by securing lower power consumption and wider operating voltage range.
128-Segment and 64-Common Outputs LCD Driver IC with A Built-in RAM
* Abundant command functions - Display data read/write - Setting up LCD alternating signal cycle - Setting up display starting-line : per line - Display ON/OFF - Display control of normal and reverse modes - Increment control of display RAM address - Write control of read modifying - Internal register read - Power saving mode * LCD drive power circuit - Built-in booster circuit : Two, three or four times voltage boost is possible - Built-in voltage converter : Generates LCD drive voltages (V0, V1, V2, V3 and V4) based on the boosted voltage - Built-in power bias ratio : 1/7 or 1/9 bias (selectable by command) - Built-in electronic volume : Controllable in 16 steps - Supply voltages Logic system : +1.8 to +5.5 V LCD drive system : +4.0 to +14.0 V * Operating temperature : -30 to +85 C * Package : 260-pin TCP (Tape Carrier Package)
FEATURES
* * * * Graphic display output pin : 64 x 128 pins Segment display output pin : 3 x 12 pins Icon display output pin : 1 x 1 pin LCD display by graphic display RAM - Normal mode : RAM data "0"/not lighted, RAM data "1"/lighted - Reverse mode : RAM data "1"/not lighted, RAM data "0"/lighted Display RAM memory capacity - 128 x 64 = 8 192 bits (For graphic display) - 12 x 3 = 36 bits (For segment display) - 1 x 1 = 1 bit (For icon display) General 8-bit MPU interface : Possible to directly connect 80-family and 68-family MPUs to bus line Possible to make serial interface Ratio of display duty cycle : 1/16, 1/32, 1/48 or 1/64 (selectable by command) 128-bit automatic transfer from display RAM to display data latch
*
* * * *
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH155BA
PIN CONNECTIONS
260-PIN TCP
ICON1 1 ICON2 COMS0 COMS1 COMS2 SEGS0 SEGS1
TOP VIEW
SEGS10 SEGS11 COM31 COM30
COM1 COM0 SEG0 SEG1 SEG2
SEG125 SEG126 SEG127 COM32 COM33
260 VA VB VC VD VR2 VR1 VOUT VEE3 SVOUT VEE2 SVR CAP+ CAP- VEE VDD PMODE EXA CKS CK VSS OSCI OSCO VSS M FLM LP D7 D6 D5 D4 D3 D2 D1 D0 RDB WRB SCL SDA P/S M86 M/S RS CSB RESB TEST VSS V4 V3 V2 V1 210 V0
COM62 COM63 209
NOTE :
Doesn't prescribe TCP outline.
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CHIP SURFACE
LH155BA
BLOCK DIAGRAM
SEGS11 COMS0 COMS2 SEG127 SEGS0 COM31 COM32 COM63 ICON1 FLM DISPLAY LINE REGISTER DISPLAY TIMING GENERATOR M LP ICON ICON2 2 COM0 49 LINE ADDRESS DECODER SEG0 50
3
5
6
17
177
18 178 209 1
VA 260 VB 259 VC 258 VD 257 V0 210 V1 211 V2 212 V3 213 Y ADDRESS REGISTER Y ADDRESS COUNTER V4 214 VSS 215 VSS 238 VSS 241 CAP+ 249 CAP- 248 VEE2 251 VEE3 253 SVOUT 252 VOUT 254 VEE 247 PMODE 245 VR1 255 VR2 256 SVR 250 ELECTRONIC VOLUME AC CONVERSION CONTROL X ADDRESS REGISTER BUS HOLDER COMMAND DECODER X ADDRESS COUNTER LCD POWER SUPPLY DC-DC CONVERTER Y ADDRESS DECODER SEGMENT DATA LATCH SEGMENT DRIVER
COMMON DRIVER SHIFT REGISTER
DISPLAY RAM 64 x 128 BITS (FOR GRAPHIC) 3 x 12 BITS (FOR SEGMENT)
X ADDRESS DECODER I/O BUFFER
REGISTER READ CONTROL
VDD 246 I/O BUFFER MPU INTERFACE OSC
227 228 229 230 231 232 233 234 216 224 223 222 217 225 226 221 220 219 218 242 243 239 240 244 237 236 235 M86 TEST RESB OSCO OSCI SCL WRB RDB SDA M/S P/S D0 D1 D2 D3 D4 D5 D6 D7 RS CSB CK CKS EXA
3
DISPLAY LINE COUNTER
LH155BA
1. PIN DESCRIPTION 1.1. Power Supply Pins
SYMBOL VDD VSS I/O DESCRIPTION Power Supply Power supply pin for logic, connected to +1.8 to +5.5 V. Power Supply Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage. V0 V1 V2 V3 V4 VA VB VC VD Power Supply V0-V4 for Graphic Display VA-VD for Segment Display * When using an external power supply, convert impedance by using resistancedivision of LCD drive power supply or operational amplifier before adding voltage to the pins. * When using the external power supply, maintain the following power supply conditions. VSS < V4 < V3 < V2 < V1 < V0, VSS VD < VC < VB < VA * When the power supply circuit is ON at master operation, LCD drive voltages of V0 to V4 are generated by the internal booster circuit and voltage converter. When using segment display, input VA, VB, VC and VD level externally. * When using the internal power supply, be sure to connect each capacitor between V0 to V4, VA to VD, and VSS.
1.2. LCD Power Supply Circuit Pins
SYMBOL CAP+ CAP- VEE2 VEE3 VEE VOUT SVOUT VR1 VR2 SVR PMODE I/O O O O O Power supply DESCRIPTION Connecting pin for the internal booster's capacitor + side. The capacitor is connected between CAP- and CAP+. Connecting pin for the internal booster's capacitor - side. The capacitor is connected between CAP+ and CAP-. Connecting pin for the internal booster's capacitor + side. The capacitor is connected between VSS and VEE2. Connecting pin for the internal booster's capacitor + side. The capacitor is connected between VSS and VEE3. Voltage supply pin for generating boosted voltage in the internal booster circuit. Usually the same voltage level as VDD. The capacitor must be connected between VSS and VOUT. Non-connected. Used as input pins for graphic display voltage converter. Voltage must be input between the VEE and VOUT pins by voltage divided by resistors. Non-connected. Pin for controlling LCD power supply. A combination of PMODE pin and ON/OFF command of power supply (PON) enables selection of a specific drive operation.
Power supply/ Output pin of boosted voltage in the internal booster circuit. O - I - I
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LH155BA
1.3. System Bus Pins
SYMBOL D7-D0 CSB RS I/O I/O I I DESCRIPTION 8-bit bi-directional data bus, connected to 8-bit MPU data bus. Chip selection input pin that decoded address bus signal is input. Distinguishes display RAM data/commands of D7 to D0 data transferred from MPU. 0 : The data of D7 to D0 show the display RAM data. 1 : The data of D7 to D0 show the command data. Initialized by setting to "L". The reset signals of the system are normally input. Reset operation is performed in accordance with RESB signal level. * In connecting to 80-family MPU : This RDB is a pin for connecting the RDB signal of 80-family MPU. When the signal enters in the "L" state, the data bus of this IC turns to the "output" state. I * In connecting to 68-family MPU : This RDB becomes a pin for connecting the enable clock signal of 68-family MPU. When the signal enters in the "H" state, the data bus of this IC turns to the "active" state. * In connecting to 80-family MPU : This WRB is a pin for connecting the WRB signal of 80-family MPU, and when WRB signal is "L", this pin is "active". WRB (R/W) The data bus signal is input at the rising edge of WRB signal. I * In connecting to 68-family MPU : This WRB becomes a pin for connecting the R/W signal of controlling read/write of 68-family MPU. R/W = "H" : Read R/W = "L" : Write MPU interface-type shift pin. M86 = "H" : 68-family interface M86 = "L" : 80-family interface Fixed to either "H" or "L". Serial-data input pin at time of serial interface selection. Serial clock pin at time of serial interface selection. Used to shift the SDA data by using the rising edge of SCL. SCL I Used to convert into 8-bit data by using the 8th clock at the rising edge of SCL in serial-to-parallel data processing. After data-transferring, or when making no access, be sure to set to "L". Used to shift between parallel interface and serial interface. Read/Write Serial clock P/S Chip selection Data identification Data P/S I H L CSB CSB RS RS D7-D0 SDA RDB, WRB Write only - SCL
RESB
I
RDB (E)
M86
I
SDA
I
P/S = "H" for parallel input. Fix SDA and SCL pins to either "H" or "L". P/S = "L" for serial input. Fix D7 to D0 pins to High-Z, RDB and WRB pins to either "H" or "L". TEST I For testing. Fix to "L".
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LH155BA
1.4. LCD Drive Circuit Signals
SYMBOL I/O DESCRIPTION The latching signal of display data to count up the display line counter at the rising, and to output the LCD drive signals at the falling. M/S = "H" : Output for master mode M/S = "L" : Input for slave mode I/O pin for LCD synchronous signals (first line marker). FLM I/O When FLM pin is set to "H", the display starting line address is preset in the display line counter. M/S = "H" : Output for master mode M/S = "L" : Input for slave mode I/O pin for alternating signals of LCD drive output. M I/O M/S = "H" : Output for master mode M/S = "L" : Input for slave mode Used to select either master or slave mode operation. M/S State OSC P.S.circuit LP FLM M/S I H Master Enabled Enabled Output Input Output Input L Slave Disabled Disabled Fix to "H" or "L" at this pin. Segment output pins for graphic display. According to the data of the display RAM data, non-lighted at "0", lighted at "1" (Normal mode) non-lighted at "1", lighted at "0" (Reverse mode) and, by a combination of M signal and display data, one signal level among V0, V2, V3, and VSS is selected. SEG0-SEG127 O
M Signal
LP
I/O
M Output Input
Display RAM Data
Normal Mode Reverse Mode
V2 V0
V0 V2
V3 VSS
VSS V3
Common output pins for graphic display. By a combination of the scanning data and M signals, one signal level among V0, V1, V4 and VSS is selected. Data M Output level COM0-COM63 O H L H L H H L L VSS V1 V0 V4
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LH155BA
SYMBOL I/O DESCRIPTION Common output pins for segment display. When executing SEGON command, it functions as common output pin. COMS0-COMS2 O COMS state SEG ON Display SEG OFF VSS
Segment output pins for segment display. When executing SEGON command, it functions as segment output pins. SEGS0-SEGS11 O SEGS state SEGON = "1" Display SEGON = "0" VSS
Common output pin for icon display. When executing ICON command, it functions as common icon display output pin. ICON1 O ICON1 state ICON = "1" Display ICON = "0" VSS
Data output pin for icon display. When executing ICON command, it functions as data icon display output pin. ICON2 O ICON2 state ICON = "1" Display ICON = "0" VSS
1.5. Pins for Oscillation Circuit
SYMBOL OSCI OSCO EXA I/O I O I DESCRIPTION Feedback-resistance connecting pin for the internal oscillation circuit. Input pin of icon clock. Input pin of display master clock at master mode. When using CK pin as an input of the master clock, fix OSCI pin to VSS. When using the internal oscillation circuit as the display master clock, fix CK pin to VSS. Selection input pin of display master clock at master mode. CKS = "H" : Input the external clock to CK pin. CKS = "L" : The internal oscillation circuit by using OSCI and OSCO pins is used.
* Master clock : Clock for oscillation circuit or external clock.
CK
I
CKS
I
7
LH155BA
1.6. Input/Output Circuits
VDD
I
To Internal Circuit
VSS (0 V)
Applicable pins CSB, RS, RDB, WRB, M86, M/S, P/S, SDA, SCL, EXA, OSCI, CK, CKS, PMODE, RESB, TEST
Fig. 1 Input Circuit
VDD
I
O
To Internal Circuit
VSS (0 V) VDD
Output Control Signal
Output Signal VSS (0 V)
Applicable pins OSCO, FLM, LP, M
Fig. 2 Input/Output Circuit (1)
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LH155BA
VDD
I
O
To Internal Circuit
VSS (0 V)
VSS (0 V)
Input Control Signal VDD
Output Control Signal
Output Signal VSS (0 V)
Applicable pins D7-D0
Fig. 3. Input/Output Circuit (2)
V0 Output Control Signal 1
V0
V1/V2 Output Control Signal 2
O Output Control Signal 3 VSS (0 V) V3/V4 VSS (0 V) VSS (0 V) Output Control Signal 4
Applicable pins SEG0-SEG127, COM0-COM63
Fig. 4. LCD Drive Output Circuit (Graphic Display)
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LH155BA
VA Output Control Signal 1
VA
VB Output Control Signal 2
O Output Control Signal 3 VSS (0 V) VC VSS (0 V) VD Output Control Signal 4
Applicable pins SEGS0-SEGS11, COMS0-COMS2
Fig. 5. LCD Drive Output Circuit (Segment Display)
VDD
VDD Output Control Signal 1
O Output Control Signal 2 VSS (0 V) VSS (0 V)
Applicable pins ICON1, ICON2
Fig. 6. LCD Drive Output Circuit (Icon Display)
2. FUNCTIONAL DESCRIPTION 2.1. MPU Interface
2.1.1. INTERFACE TYPE SELECTION The LH155BA transfers data through 8-bit parallel I/O (D7 to D0) or serial data input (SDA, SCL). The selection between parallel interface and serial interface is made by setting the state of P/S pin to
P/S H L I/F TYPE Parallel Serial CSB CSB CSB RS RS RS RDB RDB -
"H" or "L". When selecting serial interface, data-reading cannot be performed, but data-writing can.
WRB WRB -
M86 M86 -
SDA - SDA
SCL - SCL
DATA D7 to D0 -
2.1.2. PARALLEL INPUT The LH155BA can transfer data in parallel by directly connecting 8-bit MPU to the data bus when parallel interface is selected with P/S pin.
M86 H L MPU TYPE 68-family MPU 80-family MPU CSB CSB CSB RS RS RS
As an 8-bit MPU, either 80-family MPU interface or 68-family MPU interface is selected with M86 pin.
RDB E RDB
WRB R/W WRB
DATA D7 to D0 D7 to D0
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LH155BA
2.1.3. DATA IDENTIFICATION The LH155BA can identify the data of 8-bit data bus by combinations of RS, RDB and WRB signals.
68-FAMILY R/W 1 0 1 0 80-FAMILY RDB WRB 0 1 1 0 1 0 1 0
RS 1 1 0 0
FUNCTION Reads from internal register Writes to internal register Reads from display data RAM Writes to display data RAM
2.1.4. SERIAL INTERFACE The serial interface of LH155BA can accept inputs of SDA and SCL in the chip selection state (CSB = "L"). When not in the chip selection state, the internal shift register and counter are reset to their initial condition. Serial data SDA are input sequentially in order of D7 to D0 at the rising edge of serial clock (SCL) and are converted into 8-bit parallel data (by serial to parallel conversion) at the rising edge of the 8th serial clock, being processed in accordance with the data. The identification whether the serial data inputs (SDA) are display data or commands is judged by input to RS pin.
RS = "L" : Display data RS = "H" : Commands After completing 8-bit data transferring, or when making no access, be sure to set serial clock input (SCL) to "L". Protection of SDA and SCL signals against external noise should be taken in actual wiring. To prevent the successive recognition errors of transferring data from external noise, release the chip selection state (CSB = "H") at every completion of 8-bit data transferring.
CSB
RS
Valid
SDA
D7
D6
D5
D4
D3
D2
D1
D0
SCL 1 2 3 4 5 6 7 8
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LH155BA
2.2. Access to Display RAM and Internal Register
The LH155BA makes access to display RAM, and internal register by data bus D7 to D0, chip selection CSB pin, display RAM/register shifting RS pin, and read/write control RDB and WRB pins. When CSB is at "H", it is in non-selective state and cannot access display RAM and internal registers. When making access to them, set CSB to "L". The access to either display RAM or internal registers can be shifted by RS input. RS = "L" : Display RAM data RS = "H" : Internal command register The data of 8-bit data bus D7 to D0 are written by write-operation after address setting through MPU. The timing of write is at the rising of WRB for 80family MPU and at the falling of E for 68-family Data Write Operation
D7-D0 WRB Bus Holder WRB n n+1 n+2 n+3 n+4 n n+1 n+2 n+3 n+4
MPU respectively. Write is internally processed by intermediately placing the bus holder in the internal data bus. During data writing from MPU, the data are temporally held in the bus holder, then they are written by the time of the next cycle. Since the read sequence of display RAM data is limited, note that when address set is made, the designated address data are not output to read command immediately after the address set, but are output when the second data are read, resulting in requiring one time dummy read. Dummy read is always required one time after address set and write cycle.
Internal
Data Read Operation
WRB D7-D0 n Address Set n Address RDB *** Dummy Read n Data Read n Address n+1 Data Read n + 1 Address n+2 Data Read n + 2 Address
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LH155BA
2.3. Read of Internal Register
The LH155BA reads not only display RAM, but also the internal registers. Read addresses (0H, 2H-EH) are allotted to each internal register. In reading the internal registers, the addresses of internal registers allotted to read are written in the registers for internal register read and then are read.
WRB D7-D0 M For Register Address Set m Internal Register Data Read N For Register Address Set n Internal Register Data Read
RDB
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LH155BA
2.4. Display Mode
The LH155BA has 3 display modes. One is for graphic display mode and one is for segment display mode and the other is for icon display mode. Since 3 modes can be used independently by command, the suitable display mode can be selected to drive the device with minimum circuit for lower supply current operation.
2.4.1. GRAPHIC DISPLAY MODE This mode is built in 64 x 128 bits SRAM and 64common x 128-segment output. Graphic display's memory map is shown below. When standby mode and sleep mode, power supply circuit is stopped and output pin is specified VSS level. The memory for graphic display is accessed by 8 bits at one time. X address is from 00H to 0FH and Y address is from 00H to 3FH.
X address
00H
Y address
0FH
First Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H
00H 01H 02H 03H 04H 05H 06H 07H 08H
3AH 3BH 3CH 3DH 3EH 3FH SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127
3AH 3BH 3CH 3DH 3EH 3FH
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LH155BA
2.4.2. SEGMENT DISPLAY MODE This mode enables 3 x 12 bits memory and 3 COMS x 12 SEGS output. Segment display's memory map is below. Bias is fixed to 1/3. When display OFF, each output pin is specified VSS level. X address is from 00H to 01H, and Y address is from 40H to 42H.
Segment display mode and graphic display mode are independent of each other. When using segment display mode, lower power operation is possible. When using slave mode, input clock for segment display at EXA pin (500 Hz : Duty 50%), and this time, EXA flag (EH register : See Section 4.14. "Power Control (3) Register Set") must be fixed to "H".
COMS0
COMS1
COMS2
SEGS0
SEGS1
SEGS2
SEGS10
SEGS11
00H 40H 41H 42H SEGS0 SEGS1 SEGS2 SEGS3 SEGS4 SEGS5 SEGS6 SEGS7 SEGS8
01H
X address is 00H-01H, and Y address is 40H-42H.
SEGS9
SEGS10
SEGS11
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LH155BA
2.4.3. ICON DISPLAY MODE This mode enables 2 output pins for icon display and this mode can display 1 icon. Source are VDD and VSS. Since this mode is independent of other mode completely, when using this mode, lower power operation is possible. Waveform of this mode is below.
To display, use internal clock or external clock. When using external clock, input clock pulse to EXA pin (120 Hz : Duty 50%). When using icon display and segment display, input 500 Hz, duty 50% pulse.
VDD ICON1 ICON2 VSS VDD VSS
2.5. Display Starting Line Register
This register is for determining display starting line (usually the most upper line) corresponding to COM0 when displaying the display data RAM. The register is also used in picture-scrolling. The 6-bit display starting address is set in this register by display starting line setting command. The register is preset every timing of FLM signal variation in the display line counter. The line counter counts up being synchronized with LP input and generates line addresses which sequentially read out 128-bit data from display RAM to LCD drive circuit.
2.6. Addressing of Display RAM
Display RAM consists of 128 x 64 bits memory, and enables access in 8-bit unit to an address specified by X address and Y address from MPU. It is possible to set up the addresses X and Y so that they can increment automatically with the address control register. The increment is made every time display RAM is read or written from MPU. (See Section 4. "COMMAND FUNCTION".) Though the X direction side is selected by X address while the Y direction side by Y address, 10H-FFH in the X address are inhibited and do not have the X address set in these addresses. In the Y direction side, the 128-bit display data are internally read into the display data latch circuit at the rising of LP every one line cycle, and are output from the display data latch circuit at the falling of LP. 43H-FFH in the Y address are inhibited and do not have the Y address set in these addresses. When FLM signals being output in one frame cycle are at "H", the value in the display starting line register are preset in the line counter and the line counter counts up at the falling of LP signals. The display line address counter is synchronized with each timing signal of the LCD system to operate and is independent of address counters X and Y.
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LH155BA
2.7. Display RAM Data and LCD
One bit of display RAM data corresponds to one dot of LCD. Normal display and reverse display by REV register are set up as follows. * Normal display (REV = 0) : RAM data = "0"; not lighted RAM data = "1"; lighted * Reverse display (REV = 1) : RAM data = "0"; lighted RAM data = "1"; not lighted
2.8. Segment Display Output Order/ Reverse Set Up
The order of display outputs, SEG0 to SEG127 can be reversed by reversing access to display RAM from MPU by using REF register, to lessen the limitation on placing IC when composing an LCD module.
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LH155BA
2.9. Relationship between Display RAM and Address
(Configuration of display starting line address "00H")
X address Y address 1 01 0 D7 D0 SEG0 D6 D1 D5 D2 SEG1 SEG2
X = 0FH X = 00H X = 0EH X = 01H X = 00H X = 0FH
REF SWAP
Display starting line
Common Output
D4 D3
D3 D4
D2 D5
D1 D6
D0 D7
D7 D0
D6 D1
D5 D2
D4 D3
D3 D4
D2 D5
D1 D6
D0 D7
D7 D0
D6 D1
D5 D2
D4 D3
D3 D4
D2 D5
D1 D6
D0 D7
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
00H 01H Line address 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH SEG126 Segment Output SEG12 SEG13 SEG15 SEG124 SEG125 SEG127 SEG14 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG120 SEG121 SEG122 SEG123
37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63
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LH155BA
2.10. Display Timing Generator
The display timing generator generates a timing clock necessary for internal operation and timing pulses (LP, FLM, and M) by inputting the master clock CK or by the oscillation circuit of OSCI and OSCO. By setting up master/slave mode (M/S), the state of timing pulse pins and the timing generator changes.
Display Timing Pulse Pins and Timing Generator State M/S PIN L H MODE LP PIN M PIN FLM STATE OF TIMING PIN GENERATOR Stop of LP, M, FLM Slave Input Input Input generation circuit Operating state
2.12. Generation of The Alternating Signal (M) and The Synchronous Signal (FLM)
LCD alternating signal (M) and synchronous signal (FLM) are generated by the display clock (LP). The FLM generates alternated drive waveform to the LCD drive circuit. Normally, the FLM generates alternated drive waveform every frame unit (Msignal level is reversed every one frame). But by setting up data (n - 1) in an n-line reverse register and n-line alternating command (NLIN) at "H", n-line reverse waveform is generated. When the LH155BA is used in multi-chip, the signals of LP, FLM, and M must be sent from master side in the slave operation.
Master Output Output Output
2.11. Signal Generation to Display Line Counter, and Display Data Latching Circuit
Both the clock to the line counter and latching signals to display data latching circuit from the display clock (LP) are generated. Synchronized with the display clock, the line addresses of display RAM are generated and 128bit display data are latched to display-data latching circuit to output to the LCD drive circuit (SEG output). Readout of the display data to the LCD drive circuit is completely independent of MPU. Therefore, a MPU that has no relationship the readout operation of the display data can access it.
2.13. Display Data Latching Circuit
Display data latching circuit temporally latches display data that is output display data to LCD drive circuit from display RAM every one common period. Normal display/reverse display, display ON/OFF, and display all ON commands are operated by controlling data in the latch. And no data within display RAM changes.
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LH155BA
2.14. Output Timing of LCD Driver
Display timing at normal mode, 1/64 duty
63 LP FLM M
64
1
2
3
64
1
2
3
64
1
V0 V1 COM0
V4 VSS
V4 VSS
V0 V1 COM1 V1 V1
V4 VSS
V4
V4
V0 SEG0 V2 V3 VSS V3
V0
V0 V2 SEG1 V3 V2 V3 VSS V3 V2
SEG0 COM0 COM1
SEG1
SEG2
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LH155BA
2.15. LCD Drive Circuit
This drive circuit generates 4 levels of LCD drive voltage. The circuit has 128 segment outputs and 64 common outputs and outputs combined display data and M signal. A common drive circuit that has a shift register sequentially outputs common scan signals.
2.16. Oscillation Circuit
The frequency of this CR oscillator is controlled by the feedback resistor RF. The output from this oscillator is used as the timing signal source of the display and the boosting clock to the booster circuit. This is valid only in the master operation mode. During the slave operation mode, maintain OSCI pin at VSS and OSCO pin open (NC). When in the master operation mode and if external clock is used, maintain OSCI pin at VSS and OSCO pin open (NC), and feed the clock to CK pin. The duty cycle of the external clock must be 50%. The CKS pin selects either internal oscillation circuit or external clock.
MASTER MODE CKS L H OSC Enabled Disabled SLAVE MODE
This internal power supply is controlled by the power supply circuit ON/OFF command (PON). When the internal power supply is turned off, the booster circuit and voltage converter are also turned off. When using the external power supply, turn off the internal power supply, disconnect pins CAP+, CAP-, VEE2, VEE3, VOUT, VEE, VR1 and VR2, and keep PMODE pin at VSS. Then, feed external LCD drive voltages to pins V0, V1, V2, V3, and V4. This circuit can be changed by the state of PMODE pin.
PON PMODE 0 0 1 1 0 1 0 1 BOOSTER VOLTAGE EXTERNAL NOTE CIRCUIT CONVERTER VOLTAGE INPUT Disabled Disabled V0, V1, V2, V3, V4 1 Disabled Disabled V0, V1, V2, V3, V4 Enabled Disabled Enabled Enabled - VOUT, VR1, VR2 2 1
NOTES :
1. Because the booster circuit and voltage converter are not functioning, disconnect pins CAP+, CAP-, VEE2, VEE3, VOUT, VEE, VR1 and VR2. Apply external LCD drive voltages to corresponding pins. 2. Because the booster circuit is not functioning, disconnect pins CAP+, CAP-, VEE2, VEE3 and VEE. Derive the voltage source to be supplied to the voltage converter from VOUT pin and then output LCD drive voltage to VR1 and VR2 pins. The voltage level at VR1 and VR2 pins must be VR2 VR1 VOUT.
External External OSC Clock (CK) Clock (CK) Disabled Disabled Disabled Enabled Disabled Disabled
2.17. Power Supply Circuit
This circuit supplies voltages necessary to drive an LCD panel. This circuit is valid only in the master operation mode. The circuit consists of booster circuit and voltage converter. Boosted voltage from the booster circuit is fed to the voltage converter which converts this high input voltage into V0, V1, V2, V3 and V4 which are used for graphic display. This internal power supply should not be used to drive a large LCD panel containing many pixels or a large LCD panel that has large capacity consisting of more than one chip. Otherwise, display quality will degrade considerably. Instead, use an external power supply.
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LH155BA
2.18. Booster Circuit
Setting BS register, booster circuit multiple can be selected. Placing capacitor C1 across CAP+ and CAP-, across VEE2 and VSS, across VEE3 and VSS and across VOUT and VSS boosts four times. Placing capacitor C1 across CAP+ and CAP-, across VEE2 and VSS, across VOUT and VSS, and setting VEE3 to NC when boosting three times. Placing C1 across CAP+ and CAP-, across VOUT and VSS, and setting VEE2 and VEE3 to NC when boosting two times. The boosted voltage is output to VOUT pin. Since the booster circuit uses the clock derived from the internal oscillation circuit or external clock as the boosting clock, the internal oscillation circuit must be enabled, or if external clock is selected, it must be fed to CK pin. The output level at the VOUT pin does not exceed the recommended maximum operating voltage (14.0 V) when the voltage is boosted. If this value is exceeded, the operation of the LH155BA is not covered by warranty. When boosting four times and three times, placement of capacitor is as shown below.
When Boosted Four Times CAP+ CAP- VEE2 VEE3 VOUT
When Boosted Three Times CAP+ CAP- VEE2 VEE3 VOUT
VOUT = 7.2 V VOUT = 5.4 V
VEE = 1.8 V VSS = 0 V When Boosted Three Times
VEE = 1.8 V VSS = 0 V When Boosted Four Times
If charge up of LCD drive voltage is not successful, check capacity, voltage dependency and temperature characteristics of external capacitor, and select appropriate device. When charge up is
unsuccessful, it is advisable to charge up LCD drive voltage step by step (x 2, x 3, x 4) by inputting software from external microcontroller.
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LH155BA
2.19. Voltage Control Circuit
The boosted voltage at the VOUT pin is connected to the VR1 and VR2 pins and then the LCD drive voltages (V0, V1, V2, V3, and V4) are generated via the voltage converter. The input level at the VR1 and VR2 must meet the electric potential condition of VR1 VR2. The internal electronic volume divides the electric potential between the VR1 and VR2 into 16 segments. Since the VR1 and VR2 pins have high input impedance, the input voltage levels at the VR1 and VR2 are determined by the resistance ratio of R1, R2, and R3. The current flowing between the VOUT and VSS pins is determined by the combined resistance of R1, R2, and R3. Therefore, R1, R2, and R3 must be selected in accordance with the above current as well as the input voltage levels at the VR1 and VR2. The boosted voltage at the VOUT pin originates from the voltage supplied at the VEE pin. Thus, the DC path current generated with R1, R2, and R3 connected between the VOUT and VSS pins is supplied as current at the VEE pin. The electric current value, four times larger than the DC path current generated between the VOUT and VSS pins when the voltage is boosted four times, is added as supply current at the VEE pin (three times larger current is added for tripled voltage). Take sufficient care that the input levels at the VR1 and VR2 pins do not fluctuate with external noise (connect capacitor C3).
2.20. Electronic Volume
The voltage converter incorporates an electronic volume, which allows the LCD drive voltage level V0 to be controlled with a command and also allows the tone of LCD to be controlled. If 4-bit data is stored in the register of the electronic volume, one level can be selected among 16 voltage values for the LCD drive voltage V0. The voltage control range of the electronic volume is determined by the input voltage levels at the VR1 and VR2. This means that the voltage range of (VR1 to VR2) for the graphic display voltage control circuit is the controllable voltage range of the electronic volume. The electric potential relation between the VR1 and VR2 pins must be VR1 VR2. The input voltage levels at the VR1 and VR2 must be selected in accordance with the voltage levels to be obtained with the electronic volume.
2.21. LCD Drive Voltage Generation Circuit
The voltage converter contains the voltage generation circuit. The LCD drive voltages other than V0, that is, V1, V2, V3 and V4, are obtained by dividing V0 through a resistor network. The LCD drive voltage from LH155BA is biased at 1/7 or 1/9 for the graphic display mode and at 1/3 (fixed) for the segment display mode. When using the internal power supply, connect a stabilizing capacitor C2 to each of pins V0 to V4. The capacitance of C2 should be determined while observing the LCD panel to be used. In this case, connect a capacitor C3 to stabilize input voltage to VR1 and VR2. A value of C3 can be defined selectively.
C1 R1 C3 R2 C3 R3
VOUT LH155BA VR1
VR2
VSS
Example of Voltage Control Circuit
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LH155BA
2.22. Example of Power Supply Circuit Connection
VDD VDD VEE CAP+ C1 CAP- VEE2 VEE3 VSS VOUT VR1 VR2 VSS V0 V1 V2 V3 V0 V1 V2 V3 V4 VA VB VC VD OSCI RF OSCO CKS When Using The External Power Supply RF OSCO CKS When Using The Internal Power Supply VSS C1 VSS C3 VSS C3 VSS R1 VR1 R2 VR2 R3 VSS VSS V0 C2 V1 C2 V2 C2 V3 C2 V4 C2 VA VA VB VC VD OSCI CAP- VEE2 VEE3 VOUT VDD VDD VEE CAP+
C1 C1
External Power Supply
V4 VA VB VC VD
External Power Supply
VB VC VD
Recommended Values
C1 C2 C3 RF R1 + R2 + R3 1.0 to 5.0 F (B)* 1.0 to 2.0 F (B)* 0.01 to 0.1 F 680 k$ 2.0 to 4.0 M$
* B characteristics must be used with C1 and C2.
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LH155BA
2.23. Initialization
The LH155BA is initialized by setting RESB pin to "L". Normally, RESB pin is initialized together with MPU by connecting to the reset pin of MPU. When power is ON, be sure to reset operation.
PARAMETER Display RAM X-address Y-address Display starting line Display ON/OFF Display normal/reverse Display duty n-line alternating Common shift direction Increment mode REF mode Data SWAP mode Register in electronic volume Power supply INITIAL STATE Not fixed 00H set 00H set Set at the first line (0H) Display OFF Normal 1/64 Every frame unit COM0/COM63 Increment OFF Normal OFF (1, 1, 1, 1) OFF
3. PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows. q When using an external power supply o When connecting the power supply After connecting the logic system power supply, make reset operation and then apply external LCD drive voltages to corresponding pins. (V0, V1, V2, V3, V4 or VOUT, VR1 and VR2) o When disconnecting the power supply After executing HALT command, disconnect external LCD drive voltages and then disconnect the logic system power supply. w When using the internal power supply o When connecting the power supply After connecting the logic system power supply, make reset operation and then execute PON command. o When disconnecting the power supply After executing HALT command, disconnect the logic system power supply. It is advisable to connect the serial resistor (50 to 100 $) or fuse to the LCD drive power VOUT or V0 of the system as a current limiter. Set up a suitable value of the resistor in consideration of the display grade.
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LH155BA
4. COMMAND FUNCTION 4.1. Command Function Table
INSTRUCTION Display data write Display data read X address set [0H] Y address set (Lower) [2H] Y address set (Upper) [3H] Display starting line set (Lower) [4H] Display starting line set (Upper) [5H] n-line alternating set (Lower) [6H] n-line alternating set (Upper) [7H] Display control (1) set [8H] Display control (2) set [9H] Increment control set [AH] Power control (1) set [BH] Power control (2) set [DH] Power control (3) set [EH] RE set [FH] Address set for internal register read Internal register read CODE CODE FUNCTION CSB RS WRB RDB RE D7 D6 D5 D4 D3 D2 D1 D0 00010 WRITE DATA Writes to display RAM. 00100 READ DATA Reads from display RAM. Sets X direction address in X Address 010100000 display RAM. Sets Y direction address in 010100010 Y Address display RAM. Sets Y direction address in 0 1 0 1 0 0 0 1 1 * Y Address display RAM. Display Starting Sets line address of RAM 010100100 Line making COM0 display. Display Sets line address of RAM 010100101** Starting Line making COM0 display. Sets the number of alternating 0 1 0 1 0 0 1 1 0 Alternating Line reverse line. Alternating Sets the number of alternating 010100111** reverse line. Line SHI SEG ALL ON/ 0 q FT ON ON OFF 0101 1000 ER : Segment's external source 1 * * ER IR IR : Segment source mode RE NL SW RE 010101001 w V IN AP F AIM : Increment mode selection 0 1 0 1 0 1 0 1 0 * AIM AYI AXI AYI : Y increment, AXI : X increment BI HA PO AC BIAS : 1/7 or 1/9, HALT : HALT ON 010101011 AS LT N L PON : Power ON, ACL : reset Sets electronic volume for the 010101101 DVOL graphic display. IC SEG * EXA 0 e ON PON 0101 1110 DUTY DUTY : Selects duty ratio. 1 BS1 BS0 DU1 DU0 BS : Selects boosted voltage level. 0 0 0 1 1 1 0 0 1 1 1 0 0/1 0 0 1 1 * 1 1 * 1 0 * 1 0 * * * * RE Sets RE flag. Sets address of internal register for reading. Reads out internal register.
Address for Register Read Read Data
q SHIFT : Common shift direction for the graphic display, SEGON : Segment display ON, ALLON : All graphic display ON, ON/OFF : Graphic display ON/OFF control w REV : Graphic display normal/reverse, NLIN : nline reverse ON, SWAP : Data for graphic display swap, REF : Segment output for graphic display normal/reverse
e SEGPON : Power supply for segment display (Not available now. Set to "0".), EXA : Clock for segment display external/internal, ICON : Icon display ON * mark means "Don't care". Parenthesis [ ] shows address for internal register read.
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LH155BA
The LH155BA has a lot of commands, as shown in the list of commands, and each command is explained in detail as follows. (For example X address)
RS * D7 0 D6 0 D5 0 D4 0 D3 AX3 D2 AX2 D1 AX1 D0 AX0
Data codes and command codes are defined as follows and the execution of commands must be made in the chip selection state (CSB = "L").
Command Codes
Data Codes
* RS = "0" : RAM data access (Refer to Sections 4.2. and 4.3..) RS = "1" : Register access (Refer to Sections 4.4. through 4.17..) The undefined command codes are inhibited.
4.2. Data Write to Display RAM
D7 D6 D5 D4 D3 D2 D1 D0 CSB 0 RS 0 WRB 0 RDB 1 RE 0 Display RAM Write Data
The display RAM data of 8-bit are written in the designated X and Y addresses.
4.3. Data Read to Display RAM
D7 D6 D5 D4 D3 D2 D1 D0 CSB 0 RS 0 WRB 1 RDB 0 RE 0 Display RAM Read Data
The 8-bit contents of display RAM designated in X and Y addresses are read out. Immediately after data are set in X and Y addresses, dummy read is necessary one time.
4.4. X Address Register Set
D7 0 D6 0 D5 0 D4 0 D3 AX3 D2 AX2 D1 AX1 D0 AX0 CSB 0 RS 1 WRB 0 RDB 1 RE 0
(At the time of reset : AX3 to AX0 = 0H, read address : 0H) Addresses of display RAM's X direction are set. The values of AX3 to AX0 are usable up to 00H0FH, but 10H-FFH are inhibited. When the register setting of SEG output normal/reverse is REF = "0", the data of AX3 to AX0 are addressed to display RAM as they are. When REF = "1", the data of 0FH-(AX3 to AX0)H are addressed to the display RAM.
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LH155BA
4.5. Y Address Register Set
D7 0 D6 0 D5 1 D4 0 D3 AY3 D2 AY2 D1 AY1 D0 AY0 CSB 0 RS 1 WRB 0 RDB 1 RE 0
(At the time of reset : AY3 to AY0 = 0H, read address : 2H)
D7 0 D6 0 D5 1 D4 1 D3 * D2 AY6 D1 AY5 D0 AY4 CSB 0 RS 1 WRB 0 RDB 1 RE 0
* mark means "Don't care". (At the time of reset : AY6 to AY4 = 0H, read address : 3H) Addresses of display RAM's Y direction are set. In data-setting, lower place and upper place are divided with 4 bits and 3 bits respectively. When data are set, lower place should be set first and upper place should be set second. The values of AY6 to AY0 are usable up to 00H42H, but 43H-FFH are inhibited. The addresses of 40H to 42H are for the segment display RAM.
4.6. Display Starting Line Register Set
D7 0 D6 1 D5 0 D4 0 D3 LA3 D2 LA2 D1 LA1 D0 LA0 CSB 0 RS 1 WRB 0 RDB 1 RE 0
(At the time of reset : LA3 to LA0 = 0H, read address : 4H)
D7 0 D6 1 D5 0 D4 1 D3 * D2 * D1 LA5 D0 LA4 CSB 0 RS 1 WRB 0 RDB 1 RE 0
* mark means "Don't care". (At the time of reset : LA5, LA4 = 0H, read address : 5H) The display line address is required to designate, and the designated address becomes the display line of COM0.
LA5 0 0 LA4 0 0 LA3 0 0 | 1 1 1 1 1 1 LA2 0 0 LA1 0 0 LA0 0 1
The display of LCD is displayed from the designated display starting line address to the increment direction of the line address.
LINE ADDRESS 0 1 | 63
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LH155BA
4.7. n-line Alternating Register Set
D7 0 D6 1 D5 1 D4 0 D3 N3 D2 N2 D1 N1 D0 N0 CSB 0 RS 1 WRB 0 RDB 1 RE 0
(At the time of reset : N3 to N0 = 0H, read address : 6H)
D7 0 D6 1 D5 1 D4 1 D3 * D2 * D1 N5 D0 N4 CSB 0 RS 1 WRB 0 RDB 1 RE 0
* mark means "Don't care". (At the time of reset : N5, N4 = 0H, read address : 7H) The reverse line number of LCD alternated drive is required to be set in the register. The line number possible to be set is 2 to 64 lines. The values set up by the n-line alternating register become enabled when the n-line alternated drive
N5 0 0 N4 0 0 N3 0 0 N2 0 0 | 1 1 1 1 1 1 N1 0 0 N0 0 1
command is ON (NLIN = "1"). When the n-line alternated drive command is OFF (NLIN = "0"), an alternated drive waveform which reverses by frame cycle is generated.
REVERSE LINE NUMBER - 2 | 64
4.8. Alternating Timing
(1) At The Time of n-line Alternating OFF (in case of 1/64 duty display)
1st Line 2nd Line 3rd Line 64th Line 1st Line 2nd Line
LP
FLM
M
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LH155BA
(2) At The Time of n-line Alternating ON
n-line Alternate 1st Line 2nd Line 3rd Line n-th Line 1st Line 2nd Line
LP
M
4.9. Display Control (1) Register Set
D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 SHIFT SEGON ALLON ON/OFF CSB 0 RS 1 WRB 0 RDB 1 RE 0
(At the time of reset : (SHIFT, SEGON, ALLON, ON/OFF) = 0H, read address : 8H) Various controls of display are set up. (1) ON/OFF Command (For the graphic display only) To control ON/OFF of the graphic display. ON/OFF = "0" : Display OFF ON/OFF = "1" : Display ON (2) ALLON Command (For the graphic display only) Regardless of the data of the graphic display RAM, all the graphic displays are ON. This command has priority over display normal/reverse commands. ALLON = "0" : Normal display ALLON = "1" : All displays lighted.
D7 1 D6 0 D5 0 D4 0 D3 * D2 * D1 ER
(3) SEGON Command (For the segment display only) To control ON/OFF of the segment display. SEGON = "0" : Display OFF The pins are specified VSS level. SEGON = "1" : Display ON (4) SHIFT Command (For the graphic display only) The shift direction of the graphic display scanning data in the common drive output is selected. SHIFT = "0" : COM0/COM63 shift-scan SHIFT = "1" : COM63/COM0 shift-scan
D0 IR CSB 0 RS 1 WRB 0 RDB 1 RE 1
* mark means "Don't care". (At the time of reset : (ER, IR) = 0H, read address : 8H) (1) IR Command (For the segment display only) IR command is not available now. When using the segment display, set to "0". (2) ER Command (For the segment display only) ER command is not available now. When using the segment display, set to "1".
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LH155BA
And when using the segment display, input VA, VB, VC and VD level externally.
VA External Power Supply VB VC VD LH155BA
4.10. Display Control (2) Register Set
D7 1 D6 0 D5 0 D4 1 D3 REV D2 D1 D0 CSB 0 RS 1 WRB 0 RDB 1 RE 0 NLIN SWAP REF
(At the time of reset : (REV, NLIN, SWAP, REF) = 0H, read address : 9H) Various controls of display are set up. (1) REF Command When MPU accesses to the graphic display RAM, the relationship between X address and write data is normalized or reversed. Therefore, the order of segment drive output
ACCESS FROM MPU X ADDRESS D7-D0 D0 (LSB) nH | D7 (MSB) D0 (LSB) 1 nH | D7 (MSB) 0FH-nH
can be reversed by register setting, to lessen the limitation on placing IC when composing an LCD module.
REF
INTERNAL ACCESS X ADDRESS D7-D0 (LSB) nH | (MSB) (MSB) | (LSB)
CORRESPONDING SEG OUTPUT SEG (8 x nH) output | SEG (8 x nH + 7) output SEG (8 x (0FH - nH) + 7) output | SEG (8 x (0FH - nH)) output
0
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LH155BA
When using this command, outputs of segment display circuits are set as below. However the order of D0/D7 are not changed. When REF = "1", set X address of segment display circuits described below. 00H/0FH 01H/0EH
CORRESPONDING SEGS OUTPUT D0/D7 SEGS0/SEGS7 D0/D3 SEGS8/SEGS11 D0/D7 SEGS0/SEGS7 D0/D3 SEGS8/SEGS11
REF
ACCESS FROM MPU X ADDRESS 00H D7-D0 D0 (LSB) | D7 (MSB) D0 (LSB) | D3 (MSB) D0 (LSB) | D7 (MSB) D0 (LSB)
INTERNAL ACCESS Y ADDRESS 00H D7-D0 D0 (LSB) | D7 (MSB) 01H D0 (LSB) | D3 (MSB) 00H D0 (LSB) | D7 (MSB) D0 (LSB) 01H | D3 (MSB)
0
0
01H
1
0FH
1
0EH
| D3 (MSB)
(2) SWAP Command (For the graphic display only) When data to the graphic display RAM are written, the write data are swapped. SWAP = "0" : Normal mode. In data-writing, the data of D7 to D0 can be written to the graphic display RAM.
SWAP = "1" : SWAP mode ON. In data-writing, the swapped data of D7 to D0 can be written to the graphic display RAM.
EXTERNAL DATA INTERNAL DATA
SWAP = "0" D7 D6 D5 D4 D3 D2 D1 D0 d7 d6 d5 d4 d3 d2 d1 d0
SWAP = "1" D7 D6 D5 D4 D3 D2 D1 D0 d0 d1 d2 d3 d4 d5 d6 d7
(3) NLIN Command (For the graphic display only) The ON/OFF control of n-line alternated drive is performed. NLIN = "0" : n-line alternated drive OFF. By using frame cycle, the alternating signals (M) are reversed. NLIN = "1" : n-line alternated drive ON. According to data set up in n-line alternating register, the alternation is made.
(4) REV Command (For the graphic display only) Corresponding to the data of the graphic display RAM, the lighting or not-lighting of the display is set up. REV = "0" : When RAM data are at "H", LCD at ON voltage (normal). REV = "1" : When RAM data are at "L", LCD at ON voltage (reverse).
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LH155BA
4.11. Increment Control Register Set
D7 1 D6 0 D5 1 D4 0 D3 * D2 AIM D1 AYI D0 AXI CSB 0 RS 1 WRB 0 RDB 1 RE 0
* mark means "Don't care". (At the time of reset : (AIM, AYI, AXI) = 0H, read address : AH) The increment mode is set up when accessing the graphic display RAM. (The graphic display RAM only) By AIM, AYI, and AXI registers, the setting-up of increment operation/non-operation for the Xaddress counter and the Y-address counter every write access or every read access to the graphic display RAM is possible. In setting to this control register, the increment operation of address can be made without setting
AIM 0 1
successive addresses for writing data or for reading data to the graphic display RAM from MPU. After setting this register, be sure to set the X and Y address registers. Because it is not assuring the data of X and Y address registers after setting increment control registers, the increment control of X and Y addresses by AIM, AYI and AXI registers is as follows.
SELECTION OF INCREMENT TIMING When writing to graphic display RAM or reading from graphic display RAM Only when writing to graphic display RAM (read modify)
REFERENCE q w
q This is effective when subsequently writing and reading the successive address areas. w This is effective in the case that, after reading and writing the successive address areas for every address, the read data are modified to write.
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LH155BA
AYI 0 0 1 1 AXI 0 1 0 1 SELECTION OF INCREMENT ADDRESS Increment is not made X address automatic increment Y address automatic increment X and Y addresses cooperative, automatic increment REFERENCE q w e r
q Regardless of AIM, no increment for X and Y addresses. w According to the setting-up of AIM, increment or decrement for only X address. In accordance with the REF conditions of SEG normal/reverse output setting register, X address becomes as follows. * At REF = "0" (normal output), increment by loop of
00H 0FH
r According to the setting-up of AIM, cooperative variation for X and Y addresses. When the access of X address is made up to 0FH, Y address increment occurs. * At REF = "0" (normal output)
00H 0FH (X address) 00H 3FH (Y address)
vary in the above loops. * At REF = "1" (reverse output)
0FH 00H (X address) 00H 3FH (Y address)
* At REF = "1" (reverse output), decrement by loop of
0FH 00H
vary in the above loops.
e According to the setting-up of AIM, increment for only Y address. Regardless of REF, increment by loop of
00H 3FH
for Y address.
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LH155BA
4.12. Power Control (1) Register Set
D7 1 D6 0 D5 1 D4 1 D3 D2 D1 PON D0 ACL CSB 0 RS 1 WRB 0 RDB 1 RE 0 BIAS HALT
(At the time of reset : (BIAS, HALT, PON, ACL) = 0H, read address : BH) (1) ACL Command The internal circuit can be initialized. This command is enabled only at master operation mode. ACL = "0" : Normal operation ACL = "1" : Initialization ON If the power control register is read out immediately after executing ACL command (ACL = 1), the D0 bit is in the state of "1". Therefore, if the reset operation is internally started, the D0 bit becomes "0". In executing ACL command, the internal reset signals are internally generated by using display master clock (oscillation by OSCI and OSCO, or clock input at CK pin). Therefore, after executing ACL command, allow a waiting period having at least a two-cycle portion of the master clock before the next processing is made. (2) PON Command The internal power supply for the graphic display circuit is set ON/OFF. PON = "0" : Power supply for the graphic display circuit OFF PON = "1" : Power supply for the graphic display circuit ON At PON = "1", the booster circuit and voltage converter for the graphic display circuit function. In accordance with the setting conditions of PMODE pin, the operation circuit part changes. See Table in Section 2.17. for details. (3)HALT Command The conditions of power-saving are set ON/OFF by this command. HALT = "0" : Normal operation HALT = "1" : Power-saving operation When setting in the power-saving state, the supply current can be reduced to a value near to that of the standby current. The internal conditions at power-saving are as follows. (a) The oscillation circuit and power supply circuit are stopped. (b) The LCD drive is stopped, and outputs of the segment driver and common driver are VSS level. (c) The clock input from CK pin is inhibited. (d) The contents of the display RAM data are maintained. (e) The operation mode maintains the command execution state before executing powersaving command. (4) BIAS Command The internal bias value for the graphic display can be set by this command. BIAS = "0" : 1/9 bias BIAS = "1" : 1/7 bias (Bias value for the segment display is 1/3 fixed.)
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LH155BA
4.13. Power Control (2) Register Set
Electronic volume for the graphic display.
D7 1 D6 1 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 WRB 0 RDB 1 RE 0 MSB LSB
(At the time of reset : (DVOL) = 0H, read address : DH) The LCD drive voltage V0 output from the internal power supply circuit can be controlled and the display tone on the LCD can be also controlled. The LCD drive V0 takes one out of 16 voltage values by setting a 4-bit data register. If the electronic volume is not used, specify (1, 1, 1, 1) in the 4-bit data register. After the LH155BA is reset, the 4-bit data register is automatically set to (1, 1, 1, 1).
MSB LSB 0 0 0 0 | 1 1 1 1 V0 Smaller | Larger
4.14. Power Control (3) Register Set
D7 1 D6 1 D5 1 D4 0 D3 SEGPON D2 * D1 EXA D0 ICON CSB 0 RS 1 WRB 0 RDB 1 RE 0
* mark means "Don't care". (At the time of reset : (SEGPON, EXA, ICON) = 0H, read address : EH) (1) ICON Command Icon display ON/OFF. ICON = "0" : ICON is OFF. ICON = "1" : ICON is ON. See Section 2.4.3. "ICON DISPLAY MODE" for details. (2) EXA Command Clock for icon display external/internal. EXA = "0" : Internal clock EXA = "1" : External clock from EXA pin (3) SEGPON Command A power supply for the segment display is set ON/OFF. SEGPON = "0" : Power supply circuit is OFF. SEGPON = "1" : Power supply circuit is ON. SEGPON command is not available now. Set SEGPON = "0".
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LH155BA
D7 1 D6 1 D5 1 D4 0 D3 DU1 D2 DU0 D1 BS1 D0 BS0 CSB 0 RS 1 WRB 0 RDB 1 RE 1
(At the time of reset : (DU1, DU0, BS1, BS0) = 0H, read address : EH) (1) BS Command Command for bias setting. Select boost voltage level below.
BOOSTED VOLTAGE LEVEL 4 times 3 times 2 times Prohibition
(2) DUTY Command Command for duty setting. Select duty ratio below.
DU1 0 0 1 1 DU0 0 1 0 1 DUTY RATIO 1/64 1/48 1/32 1/16
BS1 0 0 1 1
BS0 0 1 0 1
Do not set BS1 = "1", BS0 = "0".
4.15. RE Register Set
D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 RE CSB 0 RS 1 WRB 0 RDB 1 RE 0/1
* mark means "Don't care". (At the time of reset : (RE) = 0H, read address : FH) RE Command RE = "0" : The power supply selection for the segment display, duty ratio selection and boosted voltage level selection cannot be accessed.
RE = "1" : The extended function is set. The power supply selection for the segment display, duty ratio selection and boosted voltage level selection can be accessed.
4.16. Address Set for Internal Register Read
D7 1 D6 1 D5 0 D4 0 D3 RA3 D2 RA2 D1 RA1 D0 RA0 CSB 0 RS 1 WRB 0 RDB 1 RE 0
(At the time of reset : (RA3, RA2, RA1, RA0) = CH) When data set up in the internal registers are read out, set the read address allotted to each register by this command before executing the read command of the internal registers. For example, when the data of the command register in the display control (1) are read out, set the values of (RA3, RA2, RA1, and RA0 ) = 8H. Refer to the functional description of each command or the list of commands for the read address allotted to each command register.
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LH155BA
4.17. Internal Register Read
D7 * D6 * D5 * D4 * D3 D2 D1 D0 CSB 0 RS 1 WRB 1 RDB 0 RE 0 Internal Register Read Data
* mark means "Don't care". Command for reading out the data of the internal registers. When this command is executed, the read address in the internal registers to be read must be preset.
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LH155BA
4.18. Example of Setting Commands
(1) Initialization
Power (VDD - VSS, VEE - VSS) ON
(3) Power OFF
A state of function
Power will be stable
Inputting RESET operation
Setting optional functions *Setting HALT command (LCD drive output VSS level)
WAIT
WAIT
Setting optional functions *Setting electronic volume maximum *Setting bias ratio 1/7
Power (VDD - VSS, VEE - VSS) OFF
Setting optional functions *Setting power control
End initialization
If VDD and VEE voltages are not same, disconnect the booster circuit power supply (VEE) first. After VEE, VOUT, V0, V1, V2, V3 and V4 voltages are below LCD ON voltage (threshold voltage for liquid crystal turns on), disconnect the logic system power supply (VDD).
If VDD and VEE voltages are not same, connect the logic system power supply (VDD) first. (2) Display Data
End initialization
Setting optional functions *Setting electronic volume *Setting bias ratio *Setting display starting line *Setting increment control *Setting X address *Setting Y address
Setting optional functions *Writing to display data
Setting optional functions *Setting display ON/OFF control
Display data
39
LH155BA
5. ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage (1) Supply voltage (2) Supply voltage (3) Supply voltage (4) Supply voltage (5) Supply voltage (6) SYMBOL VDD VEE VOUT VR V0 V1, V2, V3, V4 VI TSTG APPLICABLE PINS VDD VEE VOUT VR V0 V1, V2, V3, V4 D7-D0, CSB, RS, M/S, M86, RDB, WRB, Input voltage Storage temperature CK, CKS, OSCI, LP, FLM, M, SDA, SCL, P/S, RESB, EXA, PMODE, TEST -0.3 to VDD + 0.3 -45 to +125 V C RATING -0.3 to +6.0 -0.3 to +6.0 -0.3 to +15.0 -0.3 to +15.0 -0.3 to +15.0 -0.3 to V0 + 0.3 UNIT V V V V V V 1, 2 NOTE
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to VSS (0 V).
6. RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage SYMBOL VDD VEE V0 Operating voltage Operating temperature VOUT VR1, VR2 TOPR APPLICABLE PINS VDD VEE V0 VOUT VR1, VR2 MIN. +1.8 +2.4 +4.0 +4.0 -30 TYP. MAX. +5.5 +5.5 +14.0 +14.0 +14.0 +85 UNIT V V V V V C NOTE 1 2 3 4
NOTES :
1. The applicable voltage on any pin with respect to VSS (0 V). 2. When using the booster circuit, power supply, VEE at the primary circuit must be used within the above-described range. If the drive voltage of LCD panel can be boosted by utilizing the voltage level of VDD, usually connect this pin to VDD power supply. 3. Ensure that voltages are set such that VSS < V4 < V3 < V2 < V1 < V0. 4. The operating range is adjusted by the external circuit constructed between VOUT and VR1, VR2. The electric potential relation between the VR1, VR2 and VOUT pins must be VR2 VR1 VOUT.
40
LH155BA
7. ELECTRICAL CHARACTERISTICS 7.1. DC Characteristics
(Unless otherwise specified, VSS = 0 V, VDD = +1.8 to +5.5 V, TOPR = -30 to +85 C)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current Output leakage current LCD drive output ON resistance Standby current SYMBOL VIL VIH VOL VOH ILI ILO RON ISTB IOL = 0.4 mA IOH = -0.4 mA VI = VSS or VDD VI = VSS or VDD |VON| V0 = 10 V = 0.5 V V0 = 6 V VDD = 5 V CK = 0 V VDD = 3 V CSB = VDD VDD = 2 V During VDD = 5 V sleep VDD = 3 V mode VDD = 2 V During VDD = 5 V hold VDD = 3 V mode VDD = 2 V During VDD = 5 V active mode VDD = 3 V fCYC = 100 kHz VDD = 2 V VDD = 5 V RF = VDD = 3 V 680 k$2% VDD = 2 V CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE D7-D0, CSB, RS, M/S, M86, RDB, 0 0.2VDD V WRB, CK, CKS, OSCI, LP, FLM, M, SDA, SCL, P/S, RESB, EXA, 0.8VDD VDD V PMODE 0.4 V D7-D0, LP, FLM, M VDD - 0.4 V CSB, RS, M/S, M86, RDB, WRB, CK, CKS, OSCI, SDA, SCL, P/S, -10 10 A RESB, EXA, PMODE D7-D0, LP, FLM, M -10 10 A 1 SEG0-SEG127, 4 k$ 2 COM0-COM63 6 20 A 3 VDD 10 5 20 VDD A 4 10 5 240 120 VDD, VEE A 5 80 1 200 A 6 VDD 400 200 30 28 OSCO kHz 7 24 RESB 10 s
5. Applied when no access is made by the MPU when the internal oscillation circuit (RF = 680 k$) and power supply circuit (PMODE = "L") are used. The electronic volume is preset (the code is "1 1 1 1"). The display is OFF and the LCD drive pin is not loaded. Measuring conditions : VDD = VEE, VR1 = VR2, C1 = C2 = 1 F, R1 + R2 + R3 = 4 M$. 6. Active mode supply current. Using internal oscillation clock. Writing at fCYC the graphic display data which are reversed every one bit. No load. 7. Oscillation frequency when connecting a feedback resistor (RF) of 680 k$ between OSCI and OSCO.
Supply current (1)
IDD1
Supply current (2)
IDD2
Supply current (3)
IDD3
Oscillation frequency Reset ("L") pulse width
fOSC tRW
NOTES :
1. Applied when D7 to D0, LP, FLM, and M are in the high impedance state. 2. Resistance when 0.5 V is applied between each output pin and each power supply (V0, V1, V2, V3, V4). Applied when power is supplied at power bias ratio of 1/9 in the external power supply mode. 3. Current at the VDD pin when the master clock stops, the chip is not selected (CSB = VDD), and no load is used. All circuits stop. 4. Sleep mode supply current. Stop internal oscillation clock, using external EXA signal. Without using booster circuits. Graphic and segment displays OFF. Icon display ON. No load.
41
LH155BA
7.2. AC Characteristics
7.2.1. SYSTEM BUS READ/WRITE TIMING (80-FAMILY MPU) (Write Timing)
tAS8 CSB RS tAH8
tWRW8 WRB tDS8 D7-D0 tCYC8 tDH8
(Read Timing)
tAS8 CSB RS tAH8
tRDW8 RDB tRDH8 D7-D0 tRDD8 tCYC8
42
LH155BA
(80-family MPU Timing Characteristics)
PARAMETER Address hold time Address setup time System cycle time Read pulse width (READ) Write pulse width (WRITE) Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH8 tAS8 tCYC8 tRDW8 tWRW8 tDS8 tDH8 tRDD8 tRDH8 tR, tF CL = 15 pF CONDITIONS
(VDD = 2.7 to 5.5 V, TOPR = -30 to +85 C)
APPLICABLE PINS CSB RS RDB WRB D7-D0 D7-D0 All of above pins MIN. 60 40 450 270 100 100 40 220 10 15 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
(VDD = 2.4 to 2.7 V, TOPR = -30 to +85 C)
PARAMETER Address hold time Address setup time System cycle time Read pulse width (READ) Write pulse width (WRITE) Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH8 tAS8 tCYC8 tRDW8 tWRW8 tDS8 tDH8 tRDD8 tRDH8 tR, tF CL = 15 pF CONDITIONS APPLICABLE PINS CSB RS RDB WRB D7-D0 D7-D0 All of above pins MIN. 80 80 900 500 200 200 80 320 10 30 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
(VDD = 1.8 to 2.4 V, TOPR = -30 to +85 C)
PARAMETER Address hold time Address setup time System cycle time Read pulse width (READ) Write pulse width (WRITE) Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH8 tAS8 tCYC8 tRDW8 tWRW8 tDS8 tDH8 tRDD8 tRDH8 tR, tF CL = 15 pF CONDITIONS APPLICABLE PINS CSB RS RDB WRB D7-D0 D7-D0 All of above pins MIN. 160 160 1 800 1 000 400 400 160 640 10 30 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
43
LH155BA
7.2.2. SYSTEM BUS READ/WRITE TIMING (68-FAMILY MPU) (Write Timing)
tCYC6 E tEW6 tAS6
R/W
CSB RS tDS6 D7-D0 tDH6 tAH6
(Read Timing)
tCYC6 E tEW6
R/W
tAS6 tAH6
CSB RS
D7-D0 tRDD6 tRDH6
44
LH155BA
(68-family MPU Timing Characteristics)
PARAMETER Address hold time Address setup time System cycle time Enable pulse width (READ) Enable pulse width (WRITE) Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH6 tAS6 tCYC6 tEW6 tDS6 tDH6 tRDD6 tRDH6 tR, tF CL = 15 pF E CONDITIONS
(VDD = 2.7 to 5.5 V, TOPR = -30 to +85 C)
APPLICABLE PINS CSB RS MIN. 60 40 450 270 100 D7-D0 D7-D0 All of above pins 100 40 220 10 15 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
(VDD = 2.4 to 2.7 V, TOPR = -30 to +85 C)
PARAMETER Address hold time Address setup time System cycle time Enable pulse width (READ) Enable pulse width (WRITE) Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH6 tAS6 tCYC6 tEW6 tDS6 tDH6 tRDD6 tRDH6 tR, tF CL = 15 pF E CONDITIONS APPLICABLE PINS CSB RS MIN. 80 80 900 500 200 200 80 320 10 30 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
D7-D0 D7-D0 All of above pins
(VDD = 1.8 to 2.4 V, TOPR = -30 to +85 C)
PARAMETER Address hold time Address setup time System cycle time Enable pulse width (READ) Enable pulse width (WRITE) Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH6 tAS6 tCYC6 tEW6 tDS6 tDH6 tRDD6 tRDH6 tR, tF CL = 15 pF E CONDITIONS APPLICABLE PINS CSB RS MIN. 160 160 1 800 1 000 400 D7-D0 D7-D0 All of above pins 400 160 640 10 30 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
45
LH155BA
7.2.3. SERIAL INTERFACE TIMING
tCSS CSB tCSH
RS tASS tSLW SCL tDSS SDA tCYCS tDHS tAHS
tSHW
(VDD = 2.4 to 5.5 V, TOPR = -30 to +85 C)
PARAMETER Serial clock period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data set up time Data hold time CSB to SCL time CSB hold time Input signal rise and fall time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH tR, tF RS SDA CSB All of above pins CONDITIONS APPLICABLE PINS SCL MIN. 1 000 400 400 80 80 400 400 80 80 30 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
(VDD = 1.8 to 2.4 V, TOPR = -30 to +85 C)
PARAMETER Serial clock period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data set up time Data hold time CSB to SCL time CSB hold time Input signal rise and fall time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH tR, tF CONDITIONS APPLICABLE PINS SCL MIN. 2 000 800 800 160 160 800 800 160 160 30 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
RS SDA CSB All of above pins
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
46
LH155BA
7.2.4. DISPLAY CONTROL TIMING
tLPHW tLPLW
LP tDFLM FLM
tDFLM
tDM M
Input Timing Characteristics (Slave Mode)
PARAMETER LP "H" pulse width LP "L" pulse width FLM delay time M delay time Input signal rise and fall time SYMBOL tLPHW tLPLW tDFLM tDM tR, tF CONDITIONS
(VDD = 2.4 to 5.5 V, TOPR = -30 to +85 C)
APPLICABLE PINS LP FLM M All of above pins MIN. 80 80 -1.0 -1.0 MAX. UNIT s s s s ns
1.0 1.0 15
(VDD = 1.8 to 2.4 V, TOPR = -30 to +85 C)
PARAMETER LP "H" pulse width LP "L" pulse width FLM delay time M delay time Input signal rise and fall time SYMBOL tLPHW tLPLW tDFLM tDM tR, tF CONDITIONS APPLICABLE PINS LP FLM M All of above pins MIN. 80 80 -1.0 -1.0 MAX. UNIT s s s s ns
1.0 1.0 30
Output Timing Characteristics (Master Mode)
PARAMETER FLM delay time M delay time SYMBOL tDFLM tDM CONDITIONS CL = 15 pF
(VDD = 2.4 to 5.5 V, TOPR = -30 to +85 C)
APPLICABLE PINS FLM M MIN. 10 10 MAX. 1 000 1 000 UNIT ns ns
(VDD = 1.8 to 2.4 V, TOPR = -30 to +85 C)
PARAMETER FLM delay time M delay time SYMBOL tDFLM tDM CONDITIONS CL = 15 pF APPLICABLE PINS FLM M MIN. 10 10 MAX. 2 000 2 000 UNIT ns ns
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
47
LH155BA
7.2.5. MASTER CLOCK INPUT TIMING
tCKHW CK
tCKLW
(VDD = 2.4 to 5.5 V, TOPR = -30 to +85 C)
PARAMETER CK "H" pulse width CK "L" pulse width Input signal rise and fall time SYMBOL tCKHW tCKLW tR, tF CONDITIONS APPLICABLE PIN CK MIN. 10 10 MAX. 32 32 15 UNIT s s ns
(VDD = 1.8 to 2.4 V, TOPR = -30 to +85 C)
PARAMETER CK "H" pulse width CK "L" pulse width Input signal rise and fall time SYMBOL tCKHW tCKLW tR, tF CONDITIONS APPLICABLE PIN CK MIN. 10 10 MAX. 32 32 30 UNIT s s ns
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
8. CONNECTION EXAMPLES OF REPRESENTATIVE APPLICATIONS
(a) Connection to The 80-family MPU
1.8 to 5.5 V VCC A0 A7-A1 AE (80-family MPU) D7-D0 GND Reset input 7 Decoder RS CSB D7-D0 RDB WRB RESB VSS (LH155BA) VDD
8
48
LH155BA
(b) Connection to The 68-family MPU
1.8 to 5.5 V VCC A0 A15-A1 VMA (68-family MPU) D7-D0 E R/ GND Reset input 15 Decoder RS CSB D7-D0 RDB (E) WRB (R/W) RESB VSS (LH155BA) VDD
8
(c) Connection to The MPU with Serial Interface
1.8 to 5.5 V VCC A0 A7-A1 (MPU) PORT1 PORT2 GND Reset input SDA SCL RESB VSS 7 Decoder RS CSB (LH155BA) VDD
* When connecting multiple LH155BAs, input to each CSB pin by varying the decoder conditions of address signals.
49
LH155BA5
Film center Device center 48.175 44.86 19.00.5 [35.3] 34.3 (SL) DUMMY DUMMY V0 V1 V2 V3 V4 VSS TEST RESB CSB RS M/S M86 P/S SDA SCL WRB RDB D0 D1 D2 D3 D4 D5 D6 D7 LP FLM M VSS OSCO OSCI VSS CK CKS EXA PMODE VDD VEE CAP- CAP+ SVR VEE2 SVOUT VEE3 VOUT VR1 VR2 VD VC VB VA DUMMY DUMMY P0.6 x (55 - 1) = 32.40.04 W0.30.02 [0.8] 8.85 (SL) 14.4 (SL) 7.8 7.8 12.7 (SL)
9. PACKAGES
O2.0 (Good device hole)
0.6 (SL)
2.0 (SL)
8.1
7.80.5 30.00.05 (Holes) 2-R1.0 (SR) 0.2 O1.4 (Hole) 2-R0.7 (Hole)
[7.0]
UPILEX is a trademark of UBE INDUSTRIES, LTD..
O2.0 (SR) Sprocket center 5.62MAX. (Resin area) Chip center 19.4MAX.(Resin area) 39.8 (Backside PI) 39.2 (SL) 4.75 Flexible slit
4.2 (SR) [4.5] 4.5
[1.65]
6.8
[19.9]
50
[0.5] P0.18 x (213 - 1) = 38.160.05 W0.09 39.50.05 [41.0]
10.4 (SR)
11.90.05 [12.9]
3.0 (SL) 1.42
3.6 (Backside PI)
[2.5TYP.(2.2MIN.)]
0.2MAX. Pattern side 1.1MAX. Total DUMMY DUMMY COM63 COM62 COM33 COM32 SEG127 SEG126 SEG125
1.42 0.75MAX. Backside
0.60.02 COM30 COM31 SEGS11 SEGS10 SEGS1 SEGS0 COMS2 COMS1 COMS0 ICON2 ICON1 DUMMY DUMMY SEG2 SEG1 SEG0 COM0 COM1
0.40.02
o Tape Specification
Tape width Tape type Perforation pitch 48 mm Super wide 5 pitches
o Tape Material
Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 #7100 VLP 25 m Polyimide SSF (Unit : mm)
PACKAGES FOR LCD DRIVERS
0.60.02
0.40.02
LH155BAF
63.9490.12 Film center Device center 1.1MAX. Total 0.75MAX. Backside 0.2MAX. Pattern side O1.8 (Hole) O2.0 (Cu) DUMMY DUMMY V0 V1 V2 V3 V4 VSS TEST RESB CSB RS M/S M86 P/S SDA SCL WRB RDB D0 D1 D2 D3 D4 D5 D6 D7 LP FLM M VSS OSCO OSCI VSS CK CKS EXA PMODE VDD VEE CAP- CAP+ SVR VEE2 SVOUT VEE3 VOUT VR1 VR2 VD VC VB VA DUMMY DUMMY 27.00.7 [47.6 (E.L.)] 45.6 (SL) P0.8 x (55 - 1) = 43.20.07 W0.4 0.40.02 28.00.06
O2.0 (Good device hole)
2.0 (SL) 0.2 R0.75 (Hole) Sprocket center [3.7 (E.L.)] O1.5 (Hole) 5.62MAX. (Resin area) R1.05 (SR) Chip center [0.5 (E.L.)] O2.1 (SR)
7.00.7 [7.7 (E.L.)] 19.4MAX.(Resin area) 39.00.08 (Holes)
7.00.05
0.40.05 (Hole)
4.8 (SR)
5.1
[20.0 (E.L.)]
9.0 (SR)
11.30.05 10.60.05
0.20.02
[12.3 (E.L.)]
51
P0.25 x (209 - 1) = 52.00.07 W0.13 P0.25 x (213 - 1) = 53.00.07 W0.13 54.40.075
COM30 COM31 SEGS11 SEGS10 SEGS1 SEGS0 COMS2 COMS1 COMS0 ICON2 ICON1 DUMMY DUMMY SEG2 SEG1 SEG0 COM0 COM1
1.9810.05
4.750.05
0.7
1.9810.05
PACKAGES FOR LCD DRIVERS
0.20.02
DUMMY DUMMY COM63 COM62
COM33 COM32 SEG127 SEG126 SEG125
[56.0 (E.L.)]
0.7
[1.0]
0.260.02
o Tape Specification
Tape width Tape type Perforation pitch 70 mm Wide 5 pitches
o Tape Material
Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 E type VLP 25 m Epoxy resin

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